Non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM) and flash, etc.) are in widespread use in the industry today. Such devices are used in compact flash cards for digital cameras, memory sticks, jump drives, EEPROM chips for booting-up devices (e.g., basic input/output system (BIOS)), and many other applications. Such devices in mass production generally have cells formed by two polysilicon (“poly”) layers, where a first poly layer is used as a floating gate (FG), and a second poly layer is used as a control gate (CG). The control gate may be capacitively coupled to the floating gate using an oxide-nitride-oxide (ONO) layer, which is deposited in between the two poly layers.
Two different approaches are generally used for programming and erasing flash memory devices, and typically based on whether the flash is NAND or NOR type. In a NAND flash, memory cell programming and erasing is done using Fowler-Nordheim (F-N) tunneling through the tunnel oxide below the floating gate. In a NOR flash device, programming is done using channel hot electron (CHE) injection, while erasing is done using the Fowler-Nordheim tunneling through the tunnel oxide. However, both of these approaches suffer from increased cost and process complexity, primarily due to the second poly layer and the ONO structure. In addition, F-N tunneling generally requires high voltages (e.g., in the 14 V to 18 V range), resulting in greater power consumption, complexity, and cost (e.g., due to high voltage compatible transistors).
Other conventional approaches utilize a single poly layer in EEPROM memory cells. In these devices, the floating gate may be coupled using a well (e.g., NWELL or PWELL) or diffusion (e.g., N+ or P+), and instead of using a second poly layer to form the control gate. The program and erase functions can be performed using either hot electrons or F-N tunneling, as discussed above with reference to NAND and NOR type flash devices. One disadvantage of using well or diffusion coupling is the associated increase in area and memory cell size. Therefore, integrated circuit (IC) implementations using these approaches are typically limited to a few thousand cells before the area penalty becomes prohibitive. Further, when using N+ diffusion to couple to the floating poly gate, the N+ junction has to be optimized as relatively deep and with a large overlap to the floating poly gate to achieve good coupling. This makes it difficult to scale to shorter channel lengths and more advanced technologies.